1. Field of the Invention
The present invention relates to semiconductor process integration and, more particularly, to a method of forming a bitline contact plug with a higher part and a lower part.
2. Description of the Related Art
Continued shrink of the dimensions of integrated circuits places more imperative requirements on creating contact openings, which are applied to form contact plugs to the integrated circuits. Particularly, the dynamic random access memory (DRAM) devices require certain integration practice to achieve the fabrication of the contact plugs, especially the bitline contact plugs, of which purpose to connect CMOS devices and memory cells.
For the concern of junction leakage, some of traditional bitline contact plugs of memory cells were made of N-doped polysilicon. The polysilicon plugs would form a continuously-distributed N-type junction, which would cause relatively lower junction leakage. However, concerning the DRAMS devices with a design rule of less than 140 nm, especially in the cases of deep sub-micron DRAM devices, a material with lower electrical resistivity is needed for the cell contact plugs. In other word, N-doped polysilicon may not be a good choice for forming the bitline contact plugs at the cell region.
However, the traditional metal plugs, such as tungsten plugs, are also not a good option for forming the bitline contact plugs at the cell region. That's because the junction leakage between the metal material and the semiconductor substrate is much larger than the junction leakage in the case of polysilicon contact plugs.
Furthermore, it is also an issue in the integration process of fabricating a contact plugs to create an opening with a dimension smaller than the minimum width of the design rule. The Japanese patent with number JP07-169755 illustrated an example to achieve this goal.